diff --git a/src/cpu.rs b/src/cpu.rs
index 7c329d6..a0a43f4 100644
--- a/src/cpu.rs
+++ b/src/cpu.rs
@@ -376,7 +376,7 @@ impl Cpu {
 
     fn reg_read(&mut self, reg: u8) -> u32 {
         let reg = reg as usize;
-        if reg > self.reg.len() {
+        if reg >= self.reg.len() {
             panic!("invalid register read");
         }
         self.reg[reg]
@@ -384,7 +384,7 @@ impl Cpu {
 
     fn reg_write(&mut self, reg: u8, val: u32) {
         let reg = reg as usize;
-        if reg > self.reg.len() {
+        if reg >= self.reg.len() {
             panic!("invalid register write");
         }
         self.reg[reg] = val;